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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:20:52 11/09/2010 
-- Design Name: 
-- Module Name:    IJTAG - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSTANTS.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IJTAG is
    Port ( tdi : in  STD_LOGIC;
           sele : in  STD_LOGIC;
           shift : in  STD_LOGIC;
           update : in  STD_LOGIC;
			  capture : in STD_LOGIC;
			  reset : in STD_LOGIC;
			  clk : in STD_LOGIC;
           tdo : out  STD_LOGIC);
end IJTAG;

architecture Behavioral of IJTAG is

signal selshift, selcapt, upd, inreg0, inreg1, inreg2, outmux0_1, outmux1_1, outmux2_1 : STD_LOGIC;
signal regsout, countout : STD_LOGIC_VECTOR(DATA_SIZE_IJTAG-1 downto 0);

component IJTAG_counter
    Port( seed : in  std_logic_vector(DATA_SIZE_IJTAG-1 downto 0);
          update : in  std_logic;
          reset : in std_logic;
          count : out  std_logic_vector(DATA_SIZE_IJTAG-1 downto 0);
          clk : in  std_logic);
end component;
	 
component mux is
    Port ( in0 : in  STD_LOGIC;
           in1 : in  STD_LOGIC;
			  sel : in std_logic;
           out0 : out  STD_LOGIC);
end component;

component FF is
    Port ( fin : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           fout : out  STD_LOGIC;
			  clk : in STD_LOGIC);
end component;

begin

 tdo <= regsout(2);
 selshift <= sele and shift;
 upd <= sele and update;
 selcapt <= sele and capture;
 

	
-- purpose : this component simulate the capteurs values
-- type    : sequential
-- notice  : in muxN, N is the identification number of the monitored chain
count: IJTAG_counter
   port map(regsout, upd, reset, countout, clk);

-- purpose : The following 3 components are used together to manage one of of the monitoring chain.
--           <FF> keeps in memory the bit to be expose in the monitoring chain.
--           <muxN_0> selects between a shifted bit and another bit selected by <mux0_1>
--           <muxN_1> selects a bit between the one coming from the IJTAG component and the one already present in the FF.
-- type    : sequential
-- Bit 0
mux0_0 : mux	 
	port map(outmux0_1, tdi, selshift, inreg0);
mux0_1 : mux
	port map(regsout(0), countout(0), selcapt, outmux0_1);
FF0 : FF
port map(inreg0, reset, regsout(0), clk);

-- Bit 1
mux1_0 : mux	 
	port map(outmux1_1, regsout(0), selshift, inreg1);
mux1_1 : mux
	port map(regsout(1), countout(1), selcapt, outmux1_1);
FF1 : FF
port map(inreg1, reset, regsout(1), clk);

-- Bit 2
mux2_0 : mux	 
	port map(outmux2_1, regsout(1), selshift, inreg2);
mux2_1 : mux
	port map(regsout(2), countout(2), selcapt, outmux2_1);
FF2 : FF
port map(inreg2, reset, regsout(2), clk);

end Behavioral;

